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AquilaOS documentation
How it works, and its code
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The virt machine's interrupt controller: ARM's GICv2. More...
Go to the source code of this file.
Macros | |
| #define | GICD_CTLR 0x000 |
| #define | GICD_ISENABLER(n) |
| #define | GICD_ICENABLER(n) |
| #define | GICD_IPRIORITYR(n) |
| #define | GICD_ITARGETSR(n) |
| #define | GICD_ICFGR(n) |
| #define | GICC_CTLR 0x000 |
| #define | GICC_PMR 0x004 |
| #define | GICC_IAR 0x00C |
| #define | GICC_EOIR 0x010 |
Functions | |
| void | gic_setup (void) |
| Sets up the GIC at boot: every interrupt masked, of the same priority, and sent to CPU 0. | |
| void | gic_enable (unsigned irq) |
| Enables (unmasks) an interrupt. | |
| void | gic_disable (unsigned irq) |
| Disables (masks) an interrupt. | |
| unsigned | gic_ack (void) |
| Acknowledges the interrupt that came. | |
| void | gic_eoi (unsigned irq) |
| Tells the GIC that an interrupt has been handled (end of interrupt). | |
Variables | |
| static uintptr_t | gicd = VIRT_REG(VIRT_GICD) |
| static uintptr_t | gicc = VIRT_REG(VIRT_GICC) |
The virt machine's interrupt controller: ARM's GICv2.
References: [1] - ARM Generic Interrupt Controller Architecture Specification, version 2.0 (IHI 0048B): the distributor (GICD_*), the CPU interface (GICC_*)
The distributor takes the interrupts (SPIs, the devices'; PPIs, a CPU's own, such as its timer's) and sends them to the CPUs' interfaces. A CPU reads GICC_IAR to learn which interrupt came (which acknowledges it), and writes it to GICC_EOIR once it's handled. Every interrupt goes to the boot CPU, and all have the same priority.
Definition in file gic.c.
| #define GICC_CTLR 0x000 |
Definition at line 28 of file gic.c.
Referenced by gic_setup().
| #define GICC_PMR 0x004 |
Definition at line 29 of file gic.c.
Referenced by gic_setup().
| #define GICD_CTLR 0x000 |
Definition at line 21 of file gic.c.
Referenced by gic_setup().
| #define GICD_ICENABLER | ( | n | ) |
Definition at line 23 of file gic.c.
Referenced by gic_disable(), and gic_setup().
| #define GICD_IPRIORITYR | ( | n | ) |
| #define GICD_ISENABLER | ( | n | ) |
| #define GICD_ITARGETSR | ( | n | ) |
| unsigned gic_ack | ( | void | ) |
| void gic_disable | ( | unsigned | irq | ) |
Disables (masks) an interrupt.
| irq | its interrupt ID |
Definition at line 75 of file gic.c.
References gic_disable(), gicd, and GICD_ICENABLER.
Referenced by gic_disable(), and irq_uninstall().
| void gic_enable | ( | unsigned | irq | ) |
Enables (unmasks) an interrupt.
| irq | its interrupt ID |
Definition at line 65 of file gic.c.
References gic_enable(), gicd, and GICD_ISENABLER.
Referenced by gic_enable(), and irq_install().
| void gic_eoi | ( | unsigned | irq | ) |
| void gic_setup | ( | void | ) |
Sets up the GIC at boot: every interrupt masked, of the same priority, and sent to CPU 0.
Definition at line 38 of file gic.c.
References gic_setup(), gicc, GICC_CTLR, GICC_PMR, gicd, GICD_CTLR, GICD_ICENABLER, GICD_IPRIORITYR, GICD_ITARGETSR, and IRQ_NR.
Referenced by gic_setup(), and platform_init().
Definition at line 34 of file gic.c.
Referenced by gic_ack(), gic_eoi(), and gic_setup().
Definition at line 33 of file gic.c.
Referenced by gic_disable(), gic_enable(), and gic_setup().